The present invention relates to a matrix display apparatus, and more particularly, to a plasma addressed display apparatus.
As one type of image display apparatuses, conventionally known is a plasma addressed display apparatus that includes a flat panel essentially composed of a display cell and a plasma cell laminated together and peripheral circuits such as a signal circuit and a vertical scanning circuit. One example of such a conventional plasma addressed display apparatus is described in Japanese Laid-Open Patent Publication No. 1-217396.
FIG. 22 shows a structure of a panel of a conventional plasma addressed display apparatus, which is a flat panel structure essentially composed of a display cell 1 and a plasma cell 2 laminated together with a microsheet 3 therebetween. The plasma cell 2 includes a glass substrate 4 and plasma discharge channels 5 arranged in rows, and generates plasma discharge line-sequentially for effecting scanning. The plasma discharge channels 5 are separated from the adjacent ones by barrier ribs 6 that define spaces arranged in rows. Stripe-shaped anode electrodes (A) 7 and stripe-shaped cathode electrodes (K) 8 are formed on the inner surface of the glass substrate 4 inside the respective plasma discharge channels 5. Ionizable gas is enclosed in the spaces of the respective plasma discharge channels 5.
The display cell 1 includes a liquid crystal layer 10 as a display medium retained between an upper glass substrate 9 and the microsheet 3. Stripe-shaped color filters 12 and stripe-shaped data electrodes (P) 11 are formed on the inner surface of the glass substrate 9 in this order so as to extend in the direction intersecting with the plasma discharge channels 5. Pixels are defined at the respective intersections of the color filters 12 and the data electrodes (P) 11 with the plasma discharge channels 5 forming a shape of matrix.
The operation of the plasma addressed display apparatus shown in FIG. 22 will be described with reference to FIG. 23 that shows a portion of FIG. 22 in more detail. When a discharge pulse is applied, plasma discharge is generated in the plasma discharge channel 5 and the inside of the plasma discharge channel 5 is turned to and maintained at around an anode potential. In an equivalent circuit, a virtual electrode 20 is formed on the surface of the microsheet 3 inside the plasma discharge channel 5 and a switch 21 is turned on. A pulse application circuit 22 is a circuit for applying xe2x80x9cvideo dataxe2x80x9d between the data electrode 11 and the anode electrode 7. When the pulse application circuit 22 applies video data in synchronization with the generation of plasma discharge, video data is written in the liquid crystal layer 11 of the pixel via the microsheet 3. When the plasma discharge is terminated, the switch 21 is turned off. The plasma discharge channel 5 is put in the floating state, allowing the written video data to be retained in the pixel. The transmittance of the liquid crystal changes depending on the retained video data.
In the plasma addressed display apparatus with the above construction, if higher resolution is intended, the components of the apparatus must be miniaturized both in the horizontal (row) and vertical (column) directions. In the case of enhancing the resolution in the vertical direction, the plasma discharge channels arranged in rows must be narrowed. In order to achieve this, the barrier ribs may be narrowed. However, extremely narrowing the barrier ribs is difficult from the standpoints of the fabrication technology and the mechanical strength. If the pitch of the barrier ribs is reduced while the width of the barrier ribs is kept unchanged, the aperture ratio will lower. Moreover, the viewing angle is narrowed since tilted incident light is blocked by the height of the barrier ribs.
The present inventor, together with other co-researchers, proposed a technique for enhancing the resolution of the plasma addressed display apparatus (Japanese Patent Application No. 10-253145, which, as well as corresponding U.S. patent application Ser. No. 09/391,804 filed on Sep. 8, 1999, are herein incorporated by reference). This technique attempts to enhance the vertical resolution of the plasma addressed display apparatus without changing the width and pitch of the barrier ribs.
FIG. 24 shows a panel structure of a plasma addressed display apparatus proposed by the present inventor and co-researchers described above. The plasma addressed display apparatus of FIG. 24 is different from that of FIG. 22 in that scanning electrodes (S) 13 are used as the electrodes for plasma discharge. The scanning electrodes (S) 13 are disposed at the bottoms of the barrier ribs 6 and at positions between the adjacent barrier ribs 6.
The operation of the plasma addressed display apparatus will be described with reference to FIGS. 25A and 25B. FIG. 25A illustrates the video data write operation of the conventional plasma addressed display apparatus disclosed in the Japanese Laid-Open Patent Publication No. 1-217396 described above, and FIG. 25B illustrates the video data write operation of the high-definition plasma addressed display apparatus proposed by the present inventor and co-researchers (Japanese Patent Application No. 10-253145) employing a conventional drive method.
Referring to FIG. 25A, at timing T11, a discharge pulse is applied to a cathode K1, and video data D11 is written and retained in a plasma discharge channel including the cathode K1 and an anode A1. At timing T12 as the next scanning period, a discharge pulse is applied to a cathode K2, and video data D12 is written and retained in a plasma discharge channel including the cathode K2 and an anode A2. At timing T13 as the subsequent scanning period, video data D13 is written in a similar manner. By this series of processing at timings T11 through T13, predetermined video data are written in predetermined plasma discharge channels as shown under timing T1E. In this case, one piece of video data is written in one plasma discharge channel.
Referring to FIG. 25B, at timing T21, a discharge pulse is applied to a selected scanning electrode S1 to allow plasma discharge to be generated between the selected scanning electrode S1 and the adjacent scanning electrodes, i.e., between S0-S1 and S1-S2, and video data D21 is written and retained in a plasma discharge channel including the selected scanning electrode S1. At timing T22 as the next scanning period, a discharge pulse is applied to a selected scanning electrode S2 to allow plasma discharge to be generated between the selected scanning electrode S2 and the adjacent scanning electrodes, i.e., in regions between S1-S2 and S2-S3 that are located in different plasma discharge channels blocked by the barrier rib 6. Video data D22 is written and retained in these plasma discharge channels. At this time, focusing on the video data written in the region between the scanning electrodes S1 and S2, the video data D21 written at timing T21 is overwritten with the video data D22 at timing T22. Similarly, at timings T23, T24, T25, and T26, a discharge pulse is applied to selected scanning electrodes S3, S4, S5, and S6, and video data D23, D24, D25, and D26 are written and retained. By this series of processing at timings T21 through T26, predetermined video data are written in predetermined plasma discharge channels as shown under timing T2E. In this way, in the plasma addressed display apparatus of FIG. 24, two pieces of video data are written in one plasma discharge channel. This improves the vertical resolution of the plasma addressed display apparatus, compared with the case shown in FIG. 25A, without changing the structure such as the pitch and width of the barrier ribs.
FIG. 26 shows the entire construction of the plasma addressed display apparatus shown in FIG. 24. Referring to FIG. 26, the plasma addressed display apparatus includes a panel 201, a signal circuit 202, a vertical scanning circuit 203, a control circuit 204, an input terminal group 206, a synchronous separation circuit 207, a system microcomputer 208, and a vertical compensation circuit 210.
The panel 201 has a flat panel structure essentially composed of a plasma cell and a display cell laminated together. The plasma cell has scanning electrodes S1 to Sn arranged in rows, and the display cell has data electrodes P1 to Pm. Pixels 205 are defined at respective intersections between the scanning electrodes S1 to Sn and the data electrodes P1 to Pm. The synchronous separation circuit 207 extracts a horizontal synchronous signal and a vertical synchronous signal from video data input via the input terminal group 206, and supplies extracted various timing signals to the control circuit 204 and the system microcomputer 208. The system microcomputer 208 manages the display phase of video data when displayed on the panel 201. The control circuit 204 controls synchronization between the signal circuit 202 and the vertical scanning circuit 203. The vertical scanning circuit 203 applies a discharge pulse to the scanning electrodes S1 to Sn line-sequentially to effect scanning. The signal circuit 202 supplies video data to the data electrodes P1 to Pm in synchronization with the scanning by the vertical scanning circuit 203. The vertical compensation circuit 210 compensates a vertical high frequency component of the video data.
FIG. 27 is a block diagram of the vertical compensation circuit 210 shown in FIG. 26. FIGS. 28A and 28B are diagrammatic illustrations of the operation of the vertical compensation circuit 210. Referring to FIG. 27, the vertical compensation circuit 210 delays a signal by a scanning period unit using line memories 32 and 33. Signals obtained from the line memories 32 and 33 are subjected to various operations and then gain-adjusted by a gain circuit 39. The resultant value is added to a current signal W2 by an adder 40.
The operation of the vertical compensation circuit 210 of FIG. 27 will be described with reference to FIGS. 28A and 28B. FIG. 28A represents the state where pixels u1 to u4 having a video level 50 and pixels u5 to u8 having a video level 150 are lined in the stream of scanning periods. Assume that the pixel u4 having a video level 50 corresponds to a current signal, i.e., the pixel u4 is a focusing pixel. In this case, the signal W2 in FIG. 27 corresponds to u4, while signals W1 and W3 correspond to the pixel u5 having a video level 150 and the pixel u3 having a video level 50, respectively.
Signals obtained from the line memories 32 and 33 are multiplied by xe2x88x92xc2xc by multipliers 34 and 36 and by xc2xd by a multiplier 35. The results from the multipliers 34, 35, and 36 are summed by adders 37 and 38. An output W4 from the adder 38 is xe2x88x9225. An optimal operational value used by the gain circuit 39 is not uniquely determined but varies depending on the preference of the viewer of the plasma addressed display apparatus. In many cases, however, a value between 0 and 1 is used. Assuming that the operational value is ⅕ in this case, an output W5 from the gain circuit 39 is xe2x88x925. An adder 40 adds the value W5 to the current signal W2. As a result, an output W6 is 45. Similarly, when the pixel u5 corresponds to a current signal, the output W6 becomes 155 as a result of the operations with the preceding and subsequent signals. If the focusing pixel has the same video level as the adjacent pixels, such as the pixel u6, having no discernable change in the image from adjacent pixels, the output W6 is 150 indicating that no compensation is made.
FIG. 28B represents the results of the compensation made for the video data by the vertical compensation circuit 210. As is apparent from FIG. 28B, a compensating signal has been added to the original signal at the edge portion of an image where the pixel level shifts, such as the portion between the pixels u4 and u5, thereby emphasizing the edge portion.
The conventional high-definition plasma addressed display apparatus shown in FIG. 24 proposed by the present inventor and co-researchers has a problem of generating a phenomenon that video data within one plasma discharge channel interfere with each other. For example, at timing T2E in FIG. 25B, the video data D21 and D22, as well as the video data D23 and D24, interfere with each other. This is due to absence of a barrier rib therebetween.
The interference between video data in the plasma addressed display apparatus of FIG. 24 will be described with reference to FIGS. 29A and 29B. FIGS. 29A and 29B are diagrammatic illustrations of the display states of video data displayed on the plasma addressed display apparatus of FIG. 24, specifically showing the state where a black line such as a part of a letter is displayed on a white background in a region of eight scanning lines (L1 to L8) and ten pixels (X1 to X10). FIG. 29A shows the state intended to write and display video data. Video data in one plasma discharge channel influence each other in the vertical direction due to absence of a barrier rib therebetween as described above. That is, the brightness for white video data tends to decrease, becoming dark, and in reverse, the brightness for black video data tends to increase. As a result, as shown in FIG. 29B, two pixels, one is black and the other is white, in the same plasma discharge channel, for example, the pixel at the crossing (L5, X6) and the pixel at the crossing (L6, X6), interfere with each other, changing the original video data. This results in quality degradation of the resultant display image such as lowered sharpness and smear at edges, which may cause the viewer to feel uncomfortable.
The vertical compensation circuit 210 is unable to minimize the above disturbance due to the interference. Rather, the compensation of a vertical edge signal tends to facilitate the disturbance, making the disturbance more conspicuous. In other words, it is not possible to use a sufficiently large gain for the vertical compensation for fear of influence of the interference.
The above problem does not only arise in the plasma addressed display apparatus exemplified above, but also may arise in other line-sequential drive type matrix display apparatuses. In such a line-sequential drive type, pixels are electrically addressed independently and the display states of the pixels are electrically retained. This may cause electrical interference between rows or columns (interference between video data). Such interference is particularly significant in matrix display apparatuses employing an addressing method that makes the interference between video data especially eminent between specific rows (between continuous scanning units), such as the plasma addressed display apparatus described above.
An object of the present invention is providing matrix display apparatus and a plasma addressed display apparatus capable of minimizing interference between video data.
In relation to the above object, the present invention is in particular aimed at obtaining high-definition, high-quality images without blur or smear by detecting the degree of disturbance due to interference from the amplitudes of video data adjacent in the vertical direction in the same discharge channel, processing the detected component in an optimal manner to obtain a correction signal, and correcting the video data with the correction signal.
The matrix display apparatus of this invention includes: a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns; a plurality of row selection elements provided to correspond to the plurality of rows; a plurality of video signal supply elements provided to correspond to the plurality of columns; a scanning circuit for supplying a scanning signal sequentially to the plurality of row selection elements for line-sequential scanning of the plurality of pixels for each of the plurality of rows; and a signal generation supply circuit for generating a video signal corresponding to video data to be displayed and supplying the video signal to the plurality of video signal supply elements in synchronization with the line-sequential scanning, wherein a given first pixel of the plurality of pixels belongs to one of a plurality of row groups each having a plurality of continuous rows, and the signal generation supply circuit receives video data, corrects first video data to be displayed by the first pixel based on a predetermined correction function that includes as variables the first video data and second video data to be displayed by a second pixel belonging to a same group and a same column as the first pixel and belonging to a row different from the first pixel and depends on the relative positional relationship between at least the first pixel and the second pixel, generates a video signal corresponding to the corrected first video data, and supplies the generated video signal to the video signal supply element corresponding to the column to which the first pixel belongs.
In one embodiment, each of the plurality of row groups includes at least three continuous rows, and the correction function is a predetermined function that further includes as a variable third video data to be displayed by a third pixel belonging to a same row group and a same column as the first pixel and belonging to a row different from the first pixel and the second pixel and further depends on the relative positional relationship between the first pixel and the third pixel.
In another embodiment, the correction function is a pre-determined function that further includes as a variable third video data to be displayed by a third pixel belonging to a same row group as the first pixel, belonging to a column different from the first pixel, and located adjacent to the first or second pixel and further depends on the relative positional relationship between the first pixel and the third pixel.
In still another embodiment, the correction function is a predetermined function that further includes as a variable fourth video data to be displayed by a fourth pixel belonging to a same row group as the first pixel, belonging to a column different from the first pixel, and located adjacent to the first or second pixel and further depends on the relative positional relationship between the first pixel and the fourth pixel.
In still another embodiment, the correction function is a linear function of the first video data and the second video data.
In still another embodiment, a coefficient of the linear function by which the first video data and the second video data are multiplied is predetermined based on brightness characteristics of the plurality of pixels.
In still another embodiment, wherein the signal generation supply circuit includes an interference detection correction circuit, and the interference detection correction circuit executes the correction based on the correction function by an arithmetic operation.
In still another embodiment, the signal generation supply circuit executes the correction based on the correction function by use of a lookup table.
In still another embodiment, the matrix display apparatus further includes a plurality of plasma discharge channels each having a plurality of scanning lines running therein, wherein each of the plurality of row groups corresponds to each of the plurality of plasma discharge channels, and each of the plurality of row selection elements corresponds to each of the plurality of scanning lines.
The plasma addressed display apparatus of this invention includes: a panel having a layered structure essentially composed of a plasma cell and a display cell laminated together, the plasma cell including plasma discharge channels arranged in rows each having at least two scanning lines allocated thereto, the display cell including data electrodes arranged in columns, pixels being defined at intersections between the plasma discharge channels and the data electrodes forming a matrix; a vertical scanning circuit for effecting scanning of the panel by applying a discharge pulse sequentially to the plasma discharge channels; a signal circuit for supplying video data to the data electrodes in synchronization with the scanning; and an interference detection correction circuit for detecting correlation between video data for the scanning lines allocated to the same plasma discharge channel and correcting the video data to be supplied to the data electrodes according to the detected correlation.
In one embodiment, the interference detection correction circuit includes a line memory for accumulating video data for one scanning period required for an operation using video data of adjacent scanning lines.
In another embodiment, the interference detection correction circuit completes the operation using video data of adjacent scanning lines within the scanning lines allocated to the same plasma discharge channel.
In another embodiment, the interference detection correction circuit includes a complete control circuit that considers a possible shift of a vertical display position of video data when the video data is displayed on the plasma addressed display apparatus.
In still another embodiment, the interference detection correction circuit determines a correction amount by a lookup table method using a memory.
In still another embodiment, the interference detection correction circuit compensates a vertical high frequency gain of the video data.
In still another embodiment, the interference detection correction circuit accumulates video data for one scanning period required for extracting a vertical high component in the line memory.
In still another embodiment, the interference detection correction circuit sets an optimal gain in cooperation with a gain control circuit for correcting interference.
In still another embodiment, the interference detection correction circuit includes a noise reduction circuit for reducing noise.
In still another embodiment, the noise reduction circuit controls a reduction amount according to a noise level of the video data.
In still another embodiment, the noise reduction circuit stores noise reduction compensation characteristics in a memory.
In still another embodiment, the interference detection correction circuit determines a correction amount in consideration of electrooptical characteristics of the display cell.
In still another embodiment, the interference detection correction circuit stores the electrooptical characteristics in a memory.